Semiconductor devices are often tested to ensure their functionality. Testing may be carried out at the wafer level, prior to individual chips being diced apart and packaged. Wafer level testing may include the use of test probes that are brought into electrical contact with pads on the devices to be tested. Such testing of devices on the wafer is commonly known as “wafer sort”. Devices that fail the testing may be marked and sorted accordingly during a subsequent wafer dicing process.
A wafer sort assembly may include a number of components, including, but not limited to, a probe head coupled to a printed circuit board (PCB) that acts as a sort interface unit (SIU). The PCB is electrically coupled to a tester. The probe head may include test probes that are electrically coupled to a space transformer that is electrically coupled to the PCB. The space transformer generally serves as a pitch transfer medium from a high-density first level interconnect (FLI) to a lower density second level interconnect (SLI). The space transformer proves an electrical path between the FLI and the SLI with internal routing, through which the FLI inputs/outputs (I/Os) are routed through the space transformer and printed circuit board (PCB) to the tester. A force retainer plate (FRP) structure may be utilized to serve as datum and loading frame for the SIU.